1. Technical Field
The present disclosure generally relates to a method for fabricating a semiconductor device having e.g., a micro-machined metal-insulator semiconductor field effect transistor (“MISFET”), employing a gas phase etching step.
2. Description of the Related Art
A long-recognized important objective in the constant advancement of monolithic IC (Integrated Circuit) technology is the scaling-down of IC dimensions. Such scaling-down of IC dimensions reduces area capacitance and is critical to obtaining higher speed performance of integrated circuits. Moreover, reducing the area of an IC leads to higher yield in IC fabrication. Such advantages are a driving force to constantly scale down IC dimensions.
A common component of a monolithic IC is a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) which is fabricated on a semiconductor substrate. As generally depicted in FIG. 1, the MOSFET 10 typically includes a source region 14 and a drain region 15 spaced apart in the substrate 11 with area between the source and drain region defining a channel 11a. The MOSFET 10 further includes insulating layers 16, 18 and 20 on the substrate and a gate 22, e.g., a polysilicon gate, which is encapsulated in the insulating layers 16, 18 and 20. To create a gate structure 22 that is physically suspended above the channel region 11a, it is necessary to remove the insulating layer 16 deposited between the gate 22 and substrate 11. This is usually accomplished by employing SiO2 as the insulating material under the gate only and using a different insulating material such as, for example, SiN, for all other insulating layers formed around and encapsulating the gate 22. During fabrication of the MOSFET 10, an opening 24 is formed in the insulating layers 18 and 20 and exposing the surface of insulating layer 16 (i.e., SiO2). Next, insulating layer 16 is removed by an etching step that employs a wet etchant, e.g. HF, that dissolves and removes insulating layer 16 but does not dissolve and remove insulating layers 18 and 20 (i.e., SiN). However, the use of multiple insulation types involves specialized processing that results in a more costly and non-portable fabrication process. The use of wet etchants are also time intrusive since this etching technique often requires the use of chemicals that are difficult to use, i.e., etchants which are temperature sensitive and often highly caustic.
It would be desirable to provide a less time invasive etching technique to remove layer from under the gate of a partially fabricated MOSFET that also does not result in the use of specialized IC manufacturing processes or wet chemical etchants.